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? semiconductor components industries, llc, 2014 april, 2014 ? rev. 2 1 publication order number: ncp1592/d ncp1592 3 v to 6 v input, 6 a output synchronous buck pwm switcher with integrated fets ncp1592 is a low input voltage 6 a synchronous buck converter that integrates both 30 m high side and low side mosfets. ncp1592 is designed for space sensitive and high efficiency applications. the main features include: a high performance voltage error amplifier; an under?voltage?lockout circuit to prevent start?up until the input voltage reaches 3 v; an internally or externally programmable soft?start circuit to limit inrush currents; and a power good output monitor signal. ncp1592 is available in thermally enhanced 28?pin tssop package. features ? 30 m , 12 a peak mosfet switches for high to efficiency at 6 a continuous output source or sink current ? adjustable output voltage down to 0.891 v with 1.0% accuracy ? wide pwm frequency: fixed 350 khz, 550 khz or adjustable 280 khz to 700 khz ? synchronizable to 700 khz ? load protected by peak current limit and thermal shutdown ? integrated solution reduces board area and component count ? this is a pb?free device application ? low?v oltage, high?density distributed power systems ? high performance point of load regulation for dsps, fpgas, asics and microprocessors ? broadband, networking and optical communications infrastructure ? portable computing/notebook pcs ph agnd vbias vin boot pgnd vsense comp input output ncp1592 figure 2. typical application circuit marking diagram http://onsemi.com tssop?28 ep case 948bg see detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. ordering information figure 1. efficiency at 350 khz load current (a) efficiency 1592g alyw a = assembly location l = wafer lot y = year w = work week g = pb?free package v i = 5 v, v o = 3.3 v
ncp1592 http://onsemi.com 2 block diagram vin ? + 1.2 v falling edge deglitch hysteresis 30 mv enable comparator ? + hysteresis 160 mv vin uvlo comparator 2.95 v vin falling and rising edge deglitch thermal shutdown 150c reference vref = 0.891v _ + ? + osc adaptive dead?time and control logic ? + hysteresis 30 mv powergood comparator 0.9*vref vsense shutdown falling edge deglitch vin ? + ph leading edge blanking reg vbias vbias ilim comparator agnd shutdown ss/ena error amplifier vo pwrgd pgnd ph boot vin 3v ? 6v vsense comp rt sync figure 3. typical application circuit 35 s 100 ns 2.5 s 2.5 s internal/external slow?start (internal slow?start time = 3.35 ms) 30 m 30 m 5 a r s q pwm comparator ncp1592 ss _dis l out c o shutdown
ncp1592 http://onsemi.com 3 figure 4. pin connections agnd vsense rt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 comp pwrgd boot ph ph ph ph ph ph ph ph ph sync ss/ena vbias vin vin vin vin vin pgnd pgnd pgnd pgnd pgnd thermal pad (top view) pin description pin no. symbol description 1 agnd analog ground. return for compensation network/output divider, slow?start capacitor. vbias capacitor, rt resistor, and sync pin. connect powerpad to agnd. 2 vsense error amplifier inverting input. connect to output voltage through compensation network/output divider. 3 comp error amplifier output. connect frequency compensation network from comp to vsense. 4 pwrgd power good open drain output. high when vsense 90% v ref otherwise pwrgd is low. note that output is low when ss/ena is low or the internal shutdown signal is active. 5 boot bootstrap output. 0.022 f ~ 0.1 f ceramic capacitor is recommended to connect between boot and ph generates floating drive for the high?side fet drive. 6 ~ 14 ph phase output. junction of the internal high?side and low?side power mosfets, and output inductor. 15 ~ 19 pgnd power ground. high current return for the low?side driver and power mosfet. connect pgnd with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. a single point connection to agnd is recommended. 20 ~ 24 vin input supply for the power mosfet switches and internal bias regulator . bypass vin pins to pgnd with x5r or higher quality 10 f ceramic capacitors. 25 vbias internal bias voltage output. 0.1 f ~ 1.0 f low esr ceramic capacitor is recommended to connect between vbias to agnd. 26 ss/ena soft start/enable input/output. dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start?up time. 27 sync synchronization input. dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. when used to synchronize to an external signal, a resistor must be connected to the rt pin. 28 rt frequency setting resistor input. connect a resistor from rt to agnd to set the switching frequency. when using the sync pin, set the rt value for a frequency at or slightly lower than the external oscillator frequency.
ncp1592 http://onsemi.com 4 maximum ratings over operating free?air temperature range unless otherwise noted rating symbol min max unit main supply voltage input v in ?0.3 7 v soft start and enable voltage ss / ena ?0.3 7 v synchronization voltage sync ?0.3 7 v frequency setting voltage rt ?0.3 6 v output divided voltage sense vsense ?0.3 4 v high side drive supply voltage boot ?0.3 ph+7 v output voltage range vbias ?0.3 7 v compensation voltage comp ?0.3 7 v power good open collector voltage pwrgd ?0.3 7 v power switching node transient voltage excursion ph (note 4) ?3 10 v power switching node source current ph internally limited a compensation source current comp 0 6 ma regulated voltage source current vbias 0 6 ma power switching node sink current ph 0 12 a compensation sink current comp 0 6 ma soft start and enable sink current ss/ena 0 10 ma power good open collector sink current pwrgd 0 10 ma voltage differential agnd to pgnd ?0.3 0.3 v operating junction temperature range (note 1) t j ?40 150 c operating ambient temperature range t a ?40 85 c storage temperature range t stg ?55 150 c thermal characteristics (note 2) tssop 28?pin ep plastic package maximum power dissipation @ t a = 25 c thermal resistance junction?to?air with solder thermal resistance junction?to?air without solder p d r ja r ja 5.49 18.2 40.5 w c/w c/w lead temperature soldering (10 sec): reflow (smd styles only) pb?free (note 3) rf 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 1: the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja 2. the value of ja is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch fr?4 board with 1.5 oz. copper on the top and bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with t a = 25 c. the pcb part layout had 12 thermal vias (see recommended land pattern in applications section of this data sheet 3. 60?180 seconds minimum above 237 c. 4. 10 v transients allowed for , 10 ns. recommended operating conditions rating symbol min typ max unit input voltage v i 3 6 v operating junction temperature t j ?40 125 c
ncp1592 http://onsemi.com 5 electrical characteristics over operating free?air temperature range unless otherwise noted parameter symbol test conditions min typ max unit power supply, vin vin operation voltage v in 3 6 v quiescent current i (qsw 350) fs = 350 khz, sync 0.8 v, rt open, ph pin open 3.5 11.2 ma i (qsw 550) fs = 550 khz, sync 2.5 v, rt open, ph pin open 4.0 16 ma i (qsd) shutdown, ss / ena = 0 v 1 1.4 ma undervoltage lockout start threshold uvlor 2.95 3.0 v stop threshold uvlof 2.7 2.8 v uvlo hysteresis uvlohyst 110 160 mv rising and falling edge deglitch (note 5) uvlortd 2.5 s bias voltage output voltage v bias i vbias = 0 2.7 2.8 2.90 v output current (note 6) i vbias 100 a cumulative reference reference voltage accuracy v ref 0.882 0.891 0.900 v regulation line regulation (notes 6 and 7) i l = 3 a, f s = 350 khz, t j = 85 c 0.04 %/v i l = 3 a, f s = 550 khz, t j = 85 c 0.04 load regulation (notes 5 and 7) i l = 0 a to 6 a, f s = 350 khz, tj = 85 c 0.03 %/a i l = 0 a to 6 a, f s = 550 khz, t j = 85 c 0.03 oscillator internally set freqsync_low sync 0.8 v, rt open 280 350 420 khz freq_high sync 2.5 v, rt open 440 550 660 externally set freq180rt rt = 180 k (1% resistor to agnd) (note 5) 252 280 308 khz freq100rt rt = 100 k (1% resistor to agnd) 460 500 540 freq68rt rt = 68 k (1% resistor to agnd) (note 5) 663 700 762 high level threshold synch 2.5 v low level threshold syncl 0.8 v external synchronization pulse duration (note 5) syncmin 50 ns frequency range (note 5) syncfreq 330 700 khz ramp valley (note 5) ramp_bot 0.441 v peak?to?peak ramp amplitude (note 5) ramp_amp 1 v minimum controllable on time (note 5) min_cot 200 ns maximum duty cycle dmax 90% 5. guaranteed by design. 6. static resistive loads only. 7. specified by the circuit used in figure 14. 8. matched mosfets low?side r ds(on) production tested, high?side r ds(on) specified by design.
ncp1592 http://onsemi.com 6 electrical characteristics over operating free?air temperature range unless otherwise noted parameter unit max typ min test conditions symbol error amplifier open loop voltage gain olg 1 k comp to agnd (note 5) 90 110 db unity gain bandwidth ugbw parallel 10 k , 160 pf comp to agnd (note 5) 3 5 mhz common mode input voltage range cmivr powered by internal ldo (note 5) 0 v bias v input bias current ivsense vsense = v ref 60 250 na output voltage slew rate (positives) easrp 3.0 4.5 v/ s output voltage slew rate (negatives) easrn 2.07 3.0 v/ s pwm comparator pwm comparator propagation delay time, pwm comparator input to ph pin (excluding deadtime) compdly 10 mv overdrive (note 5) 70 85 ns slow?st art/enable enable threshold voltage enth 0.82 1.20 1.40 v enable hysteresis voltage enhys 0.03 v falling edge deglitch (note 5) en_dly 2.5 s internal soft?start time ssi 2.18 3.35 4.1 ms charge current en_ich ss/ena = 0 v 3 5 8 a discharge current en_idsch ss/ena = 1.2 v, v i = 2.7 v 2.3 3.1 5.4 ma power good power good threshold voltage vsense falling 90 %v ref power good hysteresis voltage (note 5) 3 %v ref power good falling edge deglitch (note 5) 39 s output saturation voltage pwrgd i (sink) = 2.5 ma 166 225 mv leakage current pwrgd v i = 5.5 v 3 a current limit current limit trip point v i = 3 v, output shorted (note 5) 7.2 10 a v i = 6 v, output shorted (note 5) 10 12 current limit leading edge blanking time (note 5) 100 ns current limit total response time (note 5) 200 ns thermal shutdown thermal shutdown trip point (note 5) 135 150 165 c hysteresis (note 5) 10 output power mosfets power mosfets r ds(on) high side v i = 6 v (note 8) 26 47 m v i = 3 v (note 8) 30 61 m 5. guaranteed by design. 6. static resistive loads only. 7. specified by the circuit used in figure 14. 8. matched mosfets low?side r ds(on) production tested, high?side r ds(on) specified by design.
ncp1592 http://onsemi.com 7 typical characteristics figure 5. drain?source on?state resistance vs junction temperature figure 6. drain?source on?state resistance vs junction temperature figure 7. internally set oscillator frequency vs junction temperature figure 8. externally set oscillator frequency vs junction temperature figure 9. voltage reference vs junction temperature figure 10. device power losses at t j = 125 c vs load current t j , junction temperature ( c) 36 ?40 125 ?25 ?10 5 110 95 20 35 drain source on?state resistance (m ) t j , junction temperature ( c) 32 drain source on?state resistance (m ) t j , junction temperature ( c) 750 internally set oscillator frequency (khz) 650 550 450 350 250 sync 2.5 v sync 0.8 v 800 externally set oscillator frequency (khz) 700 600 500 400 300 200 r t = 100 k r t = 68 k r t = 180 k t j , junction temperature ( c) t j , junction temperature ( c) ?40 v ref ?voltage reference (mv) 125 ?25 ?10 5 20 35 50 110 95 80 65 895 893 891 889 887 885 t j , junction temperature ( c) 01 8 7 23 6 5 4 device power losses (w) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 t j = 125 c f s = 700 khz v i = 3.3 v v i = 5 v 80 65 50 34 32 30 28 26 24 22 20 18 ?40 125 ?25 ?10 5 110 95 20 35 80 65 50 30 28 26 24 22 20 18 16 ?40 125 ?25 ?10 5 110 95 20 35 80 65 50 ?40 125 ?25 ?10 5 110 95 20 35 80 65 50 v in = 3.3 v v in = 5 v
ncp1592 http://onsemi.com 8 typical characteristics figure 11. output voltage regulation vs. input voltage figure 12. error amplifier open loop response figure 13. internal slow?start time vs junction temperature v i , nput voltage (v) 3 3.5 v ref ?voltage reference (v) 895 4 4.5 5 5.5 6 internal slow?start time (ms) 3.9 ?40 125 ?25 ?10 5 20 35 50 110 95 80 65 t j , junction temperature ( c) 893 891 889 887 885 f, frequency (hz) 110 gain (db) 140 10k 100k 1m 10m 100m 120 100 80 60 40 20 0 ?20 ?40 1k 100 160 140 120 100 80 60 40 20 0 ?20 phase margin ( ) 3.8 3.7 3.6 3.5 3.4 t a = 85 c i o = 3 a f s = 550 khz r l = 10 k c l = 160 pf t a = 25 c phase gain
ncp1592 http://onsemi.com 9 application information figure 14 shows the schematic diagram for a typical ncp1592 application. the ncp1592 (u1) can provide greater than 6 a of output current at a nominal output voltage of 3.3 v. for proper thermal performance, the exposed thermal powerpad underneath the integrated circuit package must be soldered to the printed?circuit board. figure 14. application circuit 24 16 17 15 18 19 5 6 7 8 9 10 11 12 13 14 20 21 22 23 1 2 3 4 25 26 27 28 c7 0.047 f l1 4.7 h r5 1.18 k r4 10 k c6 12 nf c5 6.8 nf c3 68 pf r1 9.76 k c9 470 f 4 v c10 470 f 4 v c11 100 pf c8 10 f c2 200 f 10 v r2 10 k c4 0.1 f c1 0.047 f vi vo pwrgd u1 ncp1592 ++ + vin vin vin vin vin ph ph ph ph ph ph ph ph ph boot pgnd pgnd pgnd pgnd pgnd powerpad rt sync ss/ena vbias pwrgd comp vsense agnd r2 3.74 k component selection input filter the input to the circuit is a nominal 5 vdc. the input filter c2 is a 220 f poscap capacitor, with a maximum allowable ripple current of 3 a. c8 provides high frequency decoupling of the ncp1592 from the input supply and must be located as close as possible to the device. ripple current is carried in both c2 and c8, and the return path to pgnd must avoid the current circulating in the output capacitors c9 and c10. feedback circuit the resistor divider network of r3 and r4 sets the output voltage for the circuit at 3.3 v. r4, along with r1, r5, c3, c5, and c6 form the loop compensation network for the circuit. for this design, a type 3 topology is used. operating frequency in the application circuit, the 350 khz operation is selected by leaving rt and sync open. connecting a 180 k to 68 k resistor between rt (pin 28) and analog ground can be used to set the switching frequency to
ncp1592 http://onsemi.com 10 280 khz to 700 khz. to calculate the rt resistor, use the equation below: r 500 khz switching frequency 100 [k ] (eq. 1) output filter the output filter is composed of a 4.7 h inductor and two 470 f capacitors. the inductor is a low dc resistance (12 m ) type, coiltronics up3b?4r7. the capacitors used are 4 v poscap types with a maximum esr of 0.040 . the feedback loop is compensated so that the unity gain frequency is approximately 25 khz. pcb layout figure 15 shows a generalized pcb layout guide for ncp1592. the vin pins are connected together on the printed?circuit board (pcb) and bypassed with a low?esr ceramic?bypass capacitor. care should be taken to minimize the loop area formed by the bypass capacitor connections, the vin pins, and the ncp1592 ground pins. the minimum recommended bypass capacitance is 10 mf ceramic capacitor with a x5r or x7r dielectric and the optimum placement is closest to the vin pins and the pgnd pins. the ncp1592 has two internal grounds (analog and power). inside the ncp1592, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. noise injected between the two grounds can degrade the performance of the ncp1592, particularly at higher output currents. however, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. therefore, separate analog and power ground traces are recommended. there is an area of ground on the top layer directly under the ic, with an exposed area for connection to the powerpad. use vias to connect this ground area to any internal ground planes. additional vias are also used at the ground side of the input and output filter capacitors. the agnd and pgnd pins are tied to the pcb ground by connecting them to the ground area under the device as shown. the only components that tie directly to the power ground plane are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the pgnd pins of the ncp1592. use a separate wide trace for the analog ground signal path. the analog ground is used for the voltage set point divider, timing resistor rt, slow?start capacitor and bias capacitor grounds. connect this trace directly to agnd (pin 1). the ph pins are tied together and routed to the output inductor. since the ph connection is the switching node, the inductor is located close to the ph pins. the area of the pcb conductor is minimized to prevent excessive capacitive coupling. connect the boot capacitor between the phase node and the boot pin as shown. keep the boot capacitor close to the ic and minimize the conductor trace lengths. connect the output filter capacitor(s) as shown between the vout trace and pgnd. it is important to keep the loop formed by the ph pins, lout, cout and pgnd as small as practical. place the compensation components from the vout trace to the vsense and comp pins. do not place these components too close to the ph trace. due to the s ize of the ic package and the device pin?out, they must be routed close, but maintain as much separation as possible while still keeping the layout compact. connect the bias capacitor from the vbias pin to analog ground using the isolated analog ground trace. if a slow?start capacitor or rt resistor is used, or if the sync pin is used to select 350 khz operating frequency, connect them to this trace.
ncp1592 http://onsemi.com 11 figure 15. recommended land pattern for 28?pin powerpad layout considerations for thermal performance for operation at full rated load current, the analog ground plane must provide an adequate heat dissipating area. a 3?inch by 3?inch plane of 1 copper is recommended, though not mandatory, depending on ambient temperature and airflow. most applications have larger areas of internal ground plane available, and the powerpad must be connected to the largest area available. additional areas on the top or bottom layers also help dissipate heat, and any area available must be used when 6 a or greater operation is desired. connection from the exposed area of the powerpad to the analog ground plane layer must be made using 0.013 inch diameter vias to avoid solder wicking through the vias. eight vias must be in the powerpad area with four additional vias located under the device package. the size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. additional vias beyond the twelve recommended that enhance thermal performance must be included in areas not under the device package.
ncp1592 http://onsemi.com 12 minimum recommended exposed copper area for powerpad, 5 mm stencils may require 10% larger area minimum recommended top side analog ground area connect pin 1 to analog ground plane in this area for optimum performance minimum recommended thermal vias: 8x 0.013 diameter inside powerpad area 4 x 0.018 diameter under device as shown. additional 0.018 diameter vias may be used if top side analog ground area is extended. figure 16. recommended land pattern for 28?pin powerpad 0.0339 0.0650 0.0500 0.0500 0.0500 0.0650 0.0339 0.3478 0.3820 0.1700 0.1340 0.0630 0.0400 0.0600 0.0150 0.0256 0.2090 0.0130 0.0180
ncp1592 http://onsemi.com 13 performance graphs figure 17. efficiency vs output current figure 18. efficiency vs output current figure 19. load regulation vs input voltage figure 20. loop response figure 21. ambient temperature vs load current figure 22. output ripple voltage 01 23 456 100 i o , output current (a) efficiency (%) v i = 5 v f = 550 khz l = 4.7 h t a = 25 c v o = 3.3 v v o = 1.8 v v o = 1.2 v 7 90 80 70 60 50 load regulation 01 2 3 4 5 6 1.004 i o , output current (a) 1.003 1.002 1.001 1 0.999 0.998 0.997 0.996 01 23 456 100 i o , output current (a) efficiency (%) v i = 3.3 v f = 550 khz l = 4.7 h t a = 25 c v o = 2.5 v v o = 1.8 v v o = 1.2 v 90 80 70 60 50 7 v i = 5 v v o = 3.3 v t a = 25 c f s = 550 khz 125 115 105 95 85 75 65 55 45 35 25 01 2 3 4 5 6 7 8 ambient temperature ( c) i l , load current (a) t a = 125 c f s = 700 khz v i = 5.0 v v i = 3.3 v
ncp1592 http://onsemi.com 14 performance graphs figure 23. line regulation vs output current figure 24. load transient response 6 a 0 a 3 a 1.002 1.0015 1.001 1.0005 1 0.9995 0.999 0.9985 0.998 i out , output current v i , input voltage (v) 4 4.5 5 5.5 6 figure 25. slow start timing figure 26 shows the schematic diagram for a reduced size, high frequency application using the ncp1592. the ncp1592 (u1) can provide up to 6 a of output current at a nominal output voltage of 1.8 v. a small size 0.56 h inductor is used and the switching frequency is set to 680 khz by r1. the compensation network is optimized for fast transient response as shown in figure 27. for good thermal performance, the powerpad underneath the integrated circuit ncp1592 needs to be soldered well to the printed?circuit board.
ncp1592 http://onsemi.com 15 figure 26. small size, high frequency design figure 27. transient response, 1.5 to 4.5 a step 26 20 27 21 22 23 24 9 10 11 12 13 14 19 28 5 6 7 8 15 25 4 3 2 1 16 17 18 r1 68.1 k c2 10 f c1 10 f c3 22 nf c4 100 nf c5 1 nf c6 150 pf r2 3.4 k c12 5.6 nf vi c11 1000 pf c7 100 nf c9 470 f c10 10 f l1 1 h vo u1 ncp1592 + vin vin vin vin vin ph ph ph ph ph ph ph ph ph boot pgnd pgnd pgnd pgnd pgnd powerpad rt sync ss/ena vbias pwrgd comp vsense agnd r3 332 r6 10 k r5 90.9 k r4 10 c2 10 f c1 10 f
ncp1592 http://onsemi.com 16 detailed description undervoltage lock out (uvlo) the ncp1592 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (vin) is insufficient. during power up, internal circuits are held inactive until vin exceeds the nominal uvlo threshold voltage of 2.95 v. once the uvlo start threshold is reached, device start?up begins. the device operates until vin falls below the nominal uvlo stop threshold of 2.8 v. hysteresis in the uvlo comparator , and a 2.5 s rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on vin. slow?start/enable (ss/ena) the slow?start/enable pin provides two functions. first, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 v. when ss/ena exceeds the enable threshold, device start?up begins. the reference voltage fed to the error amplifier is linearly ramped up from 0 v to 0.891 v in 3.35 ms. similarly, the converter output voltage reaches regulation in approximately 3.35 ms. voltage hysteresis and a 2.5? s falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. the second function of the ss/ena pin provides an external means of extending the slow?start time with a low?value capacitor connected between ss/ena and agnd. adding a capacitor to the ss/ena pin has two effects on start?up. first, a delay occurs between release of the ss/ena pin and start?up of the output. the delay is proportional to the slow?start capacitor value and lasts until the ss/ena pin reaches the enable threshold. the start?up delay is approximately: t d c (ss) 1.2 v 5 a (eq. 2) second, as the output becomes active, a brief ramp?up at the internal slow?start rate may be observed before the externally set slow?start rate takes control and the output rises at a rate proportional to the slow?start capacitor. the slow?start time set by the capacitor is approximately: t (ss) c (ss) 0.7 v 5 a (eq. 3) the actual slow?start time is likely to be less than the above approximation due to the brief ramp?up at the internal rate. during the soft?start period the output voltage is closed loop regulated from 0v to the output set voltage by slewing the reference voltage from 0 v to 0.891 v. if output voltage is not at 0 v during startup (pre-biased startup), output capacitor will be discharged by the control loop. the energy from the capacitors will flow from the output to ground and input through the low-side and high side mosfets. under extreme conditions where pre-biased voltage is high with large output capacitance mosfets can be damaged. vbias regulator (vbias) the vbias regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. a high quality, low?esr, ceramic bypass capacitor is required on the vbias pin. x7r or x5r grade dielectrics are recommended because their values are more stable over temperature. the bypass capacitor must be placed close to the vbias pin and returned to agnd. external loading on vbias is allowed, with the caution that internal circuits require a minimum vbias of 2.70 v, and external loads on vbias with ac or digital switching noise may degrade performance. the vbias pin may be useful as a reference voltage for external circuits. voltage reference the voltage reference system produces a precise v ref signal by scaling the output of a temperature stable bandgap circuit. during manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 v at the output of the error amplifier, with the amplifier connected as a voltage follower. the trim procedure adds to the high precision regulation of the ncp1592, since it cancels offset errors in the scale and error amplifier circuits. 0scillator and pwm ramp the oscillator frequency can be set to internally fixed values of 350 khz or 550 khz using the sync pin as a static digital input. if a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 to 700 khz by connecting a resistor between the rt pin and agnd and floating the sync pin. the switching frequency is approximated by the following equation, where r is the resistance from rt to agnd: switching frequency 100 k r 500 [khz] (eq. 4) external synchronization of the pwm ramp is possible over the frequency range of 330 khz to 700 khz by driving a synchronization signal into sync and connecting a resistor from rt to agnd. choose a resistor between the rt and agnd which sets the free running frequency to 80% of the synchronization signal. the following table summarizes the frequency selection configurations:
ncp1592 http://onsemi.com 17 switching frequency sync pin rt pin 350 khz, internally set float or agnd float 550 khz, internally set 2.5 v float externally set 280 khz to 700 khz float r= 180 k to 68 k externally synchronized frequency synchronization signal r = rt value for 80% of external synchronization frequency error amplifier the high performance, wide bandwidth, voltage error amplifier sets the ncp1592 apart from most dc/dc converters. the user is given the flexibility to use a wide range of output l and c filter components to suit the particular application needs. t ype 2 or type 3 compensation can be employed using external compensation components. pwm control signals from the error amplifier output, oscillator, and current limit circuit are processed by the pwm control logic. referring to the internal block diagram, the control logic includes the pwm comparator, or gate, pwm latch, and portions of the adaptive dead?time and control logic block. during steady?state operation below the current limit threshold, the pwm comparator output and oscillator pulse train alternately reset and set the pwm latch. once the pwm latch is reset, the low?side fet remains on for a minimum duration set by the oscillator pulse width. during this period, the pwm ramp discharges rapidly to its valley voltage. when the ramp begins to charge back up, the low?side fet turns off and high?side fet turns on. as the pwm ramp voltage exceeds the error amplifier output voltage, the pwm comparator resets the latch, thus turning off the high?side fet and turning on the low?side fet. the low?side fet remains on until next oscillator pulse discharges the pwm ramp. during transient conditions, the error amplifier output could be below the pwm ramp valley voltage or above the pwm peak voltage. if the error amplifier is high, the pwm latch is never reset, and the high?side fet remains on until the oscillator pulse signals the control logic to turn the high?side fet off and the low?side fet on. the device operates at its maximum duty cycle until the output voltage rises to the regulation set?point, setting vsense to approximately the same voltage as vref. if the error amplifier output is low, the pwm latch is continually reset and the high?side fet does not turn on. the low?side fet remains on until the vsense voltage decreases to a range that allows the pwm comparator to change states. the ncp1592 is capable of sinking current continuously until the output reaches the regulation set?point. if the current limit comparator trips for longer than 100 ns, the pwm latch resets before the pwm ramp exceeds the error amplifier output. the high?side fet turns off and low?side fet turns on to decrease the energy in the output inductor and consequently output current. this process is repeated each cycle in which the current limit comparator is tripped. dead?time control and mosfet drivers adaptive dead?time control prevents shoot?through current from flowing in both n?channel power mosfets during the switching transitions by actively controlling the turn?on times of the mosfet drivers. the high?side driver does not turn on until the voltage at the gate of the low?side fet is below 2 v. while the low?side driver does not turn on until the voltage at the gate of the high?side mosfet is below 2 v. the high?side and low?side drivers are designed with 300 ma source and sink capability to quickly drive the power mosfets gates. the low?side driver is supplied from vin, while the high?side driver is supplied from the boot pin. a bootstrap circuit uses an external boot capacitor and an internal 2.5 bootstrap switch connected between the vin and boot pins. the integrated bootstrap switch improves drive efficiency and reduces external component count. overcurrent protection the cycle?by?cycle current limiting is achieved by sensing the current flowing through the high?side mosfet and comparing this signal to a preset overcurrent threshold. the high side mosfet is turned off within 200 ns of reaching the current limit threshold. a 100 ns leading edge blanking circuit prevents current limit false tripping. current limit detection occurs only when current flows from vin to ph when sourcing current to the output filter. load protection during current sink operation is provided by thermal shutdown. thermal shutdown the device uses the thermal shutdown to turn off the power mosfets and disable the controller if the junction temperature exceeds 150 c. the device is released from shutdown automatically when the junction temperature decreases to 10 c below the low thermal shutdown trip point, and starts up under control of the slow?start circuit. thermal s hutdown provides protection when an overload condition is sustained for several milliseconds. with a persistent fault condition, the device cycles continuously; starting up by control of the soft?start circuit, heating up due to the fault condition, and then shutting down upon reaching
ncp1592 http://onsemi.com 18 the thermal shutdown trip point. this sequence repeats until the fault condition is removed. power?good (pwrgd) the power good circuit monitors for under voltage conditions on vsense. if the voltage on vsense is 10% below the reference voltage, the open?drain pwrgd output is pulled low. pwrgd is also pulled low if vin is less than the uvlo threshold or ss/ena is low, or a thermal shutdown occurs. when vin uvlo threshold, ss/ena enable threshold, and vsense > 90% of v ref , the open drain output of the pwrgd pin is high. a hysteresis voltage equal to 3% of v ref and a 35 s falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise. ordering information device temperature range ( c) package shipping ? NCP1592PAR2G ?40 to +125 tssop?28 ep (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1592 http://onsemi.com 19 package dimensions tssop28 9.7x4.4 ep case 948bg issue o ???? ???? 0.20 a e 15 28 14 pin one location notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b does not include dambar protrusion. dambar protrusion shall be 0.07 max at maximum material condition. dambar cannot be located on the lower radius of the foot. min- imum space between protrusion and adjacent lead is 0.07. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension d is determined at datum plane h. 5. dimension e1 does not include inter- lead flash or protrusions. inter- lead flash or protrusions shall not exceed 0.25 per side. dimension e1 is determined at datum plane h. 6. datums a and b to be determined at datum plane h. 7. a1 is defined as the vertical distance from the seating plane to the low- est point on the package body. 8. section b?b to be determined at 0.10 to 0.25 from the lead tip. e e1 b c 1 0.10 seating d c plane a a2 b 28x 0.10 a b c dim min max millimeters a ??? 1.20 a1 0.00 0.15 a2 0.80 1.05 b 0.19 0.30 b1 0.19 0.25 c 0.09 0.20 c1 0.09 0.16 d 9.60 9.80 e 6.40 bsc e1 4.30 4.50 e 0.65 bsc l 0.45 0.75 l2 0.25 bsc d2 5.21 6.17 e2 1.44 2.40 m 0 8 2x 14 tips ??? ??? 6.70 28x 0.30 28x 1.15 0.65 dimensions: millimeters 1 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended 2.70 6.47 b a top view note 5 note 6 note 6 side view note 3 note 4 c 28x 0.05 c
ncp1592 http://onsemi.com 20 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1592/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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